1. Field the Invention
The present invention relates to a semiconductor integrated circuit such as an LSI having a terminal configuration suitable for an automatic placement and wiring layout.
2. Description of Related Art
Recent high integration of LSIs requires a very long period of time for the layout design by man power, resulting in an increased design cost. With regard to the most of the LSIs excluding a certain part of general LSIs, the design by man power is unpractical. Accordingly, a layout design system is now practically used in which a standard cell having passed a logic operation test is used for placement and wiring layout by adopting an automatic placement and wiring program.
Two types of the configuration of input, output or input/output terminals conventionally used will now be described.
FIG. 1 is a plane diagram showing a conventional standard cell disclosed in Japanese Patent Application Laid-Open No. 60-7147 (1985). In FIG. 1, reference numeral 1 denotes a standard cell frame of one standard cell. Along the upper and lower sides of the standard cell frame 1 are aligned terminals 2A, 2B, 2C, 2D and 2E to be used for input, output or input/output terminals with a predetermined interval thereamong in two lines. In this conventional standard cell, polysilicon employed in the gate of an MOS transistor is used as vertical wiring, and the polysilicon is also employed in the input, output or input/output terminals.
When polysilicon is used as the vertical wiring as in this case, a resistance per unit length is comparatively high, resulting in a disadvantage in terms of the operation speed of a logic LSI.
Further, in the recent automatic placement and wiring layout system, higher integration has been achieved by the development of the semiconductor process technology so that multi layers wiring such as three- or four-layers wiring is realized, whereas two-layers wiring was conventionally used. Therefore, a standard cell can be provided with a horizontal wiring using a third metal layer, that is, the uppermost metal layer. As a result, it is possible to dispose input, output or input/output terminals around the center of the cell, which is the configuration practically used now. FIG. 2 is a schematic plane diagram showing this type of a standard cell, wherein input, output or input/output terminals 3A, 3B, 3C and 3D are horizontally aligned in a line at the center of a standard cell frame 1 with a predetermined interval thereamong. For the terminals 3A, 3B, 3C and 3D, a second metal layer, that is a metal layer underlying a third metal layer, is generally used. In certain cases, however, both the second metal layer and the third metal layer, or contacts between the second metal layer and the third metal layer are used for the terminals.
In such a conventional three-metal layers wiring system, wirings are provided by using the third metal layer in a portion where a horizontal wiring can be provided in the standard cell, and in a portion where a horizontal wiring can not be provided, wirings are provided in an external region out of the standard cell. Therefore, this system can advantageously attain automatic placement and wiring with higher integration than the aforementioned two-layers wiring system.
FIG. 3 is a schematic diagram showing a design pattern obtained by the automatic placement and wiring in a plurality of the standard cells each having the configuration as shown in FIG. 2. This design pattern is obtained by the automatic placement and wiring for a circuit shown in FIG. 4. An inverter circuit 8A includes an input terminal 4V and an output terminal 4T, and an inverter circuit 8B includes an input terminal 4S and an output terminal 4R. A NAND circuit 8C includes four input terminals 4L, 4M, 4O and 4P and an output terminal 4N, and a NAND circuit 8D includes four input terminals 4D, 4E, 4F and 4G and an output terminal 4C. An inverter circuit 8E includes an input terminal 4B and an output terminal 4A, and a NAND circuit 8F includes three input terminals 4H, 4I and 4J and an output terminal 4K. The terminals (4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L, 4M, 4N, 4O, 4P, 4S, 4T and 4V) are horizontally aligned in a line.
The input terminal 4V of the inverter circuit 8A is connected with a standard cell 41A in another cell group through a wiring 6A, and the output terminal 4T is connected with the input terminal 4M of the NAND circuit 8C through a wiring 9A. The input terminal 4P of the NAND circuit 8C is connected with the standard cell 41A through the wiring 6A, the input terminal 4L with a standard cell 41B through a wiring 6B, the input terminal 4O with a standard cell 41C through a wiring 6C, and the output terminal 4N with the input terminal 4E of the NAND circuit 8D and with the input terminal 4B of the inverter circuit 8E through a wiring 9C. The input terminal 4S of the inverter circuit 8B is connected with a standard cell 41D through a wiring 6D, and the output terminal 4R with the input terminal 4D of the NAND circuit 8D and the input terminal 4H of the NAND circuit 8F through a wiring 9B.
The input terminal 4F of the NAND circuit 8D is connected with a standard cell 41E through a wiring 6E, the input terminal 4G with a standard cell 41F through a wiring 6F, and the output terminal 4C with a standard cell 42A through a wiring 7A. The input terminal 4I of the NAND circuit 8F is connected with the standard cell 41E through the wiring 6E, the input terminal 4J with the standard cell 41F through the wiring 6F, and the output terminal 4K with a standard cell 42C through a wiring 7C. The output terminal 4A of the inverter circuit 8E is connected with a standard cell 42B through a wiring 7B.
Broken lines in FIG. 3 indicate the horizontal wirings, which use a third metal layer. Dashed lines therein indicate the vertical wirings, which use a second metal layer. In FIG. 3, contacts for connecting the second metal layer (i.e., the vertical lines) and the third metal layer (i.e., the horizontal lines) with each other are indicated as 5A through 5O.
When the input and the output terminals in the same cell row are connected with each other in the circuits shown in FIG. 3, for example, when the input terminals 4B and 4E are connected with each other, vertical wirings are drawn upward from the respective input terminals 4B and 4E by using the second metal layer, and the formed vertical wirings are connected with the wiring 9C, which is a horizontal wiring (the third metal layer), through the contacts 5A and 5D. The wiring 9C is also connected with a vertical wiring drawn upward from the output terminal 4N through the contact 5K. Further, the input terminal 4M and the output terminal 4T are connected with each other by connecting vertical wirings drawn downward from the respective terminals with the line 9A through the contacts 5J and 5N.
Further, the input terminals 4D and 4H and the output terminal 4R are connected with one another by disposing the wiring 9B on the upper side of the wiring 9C, drawing vertical wirings, which are longer than those from the input terminals 4B and 4E, upward from the input terminals 4D and 4H and the output terminal 4R, and connecting the longer vertical wirings with the wiring 9B through the contacts 5C, 5G and 5M. With regard to the connection among the respective input and output terminals with the standard cells 41A through 41F and 42A through 42C, vertical wirings are used when they are vertically connectable, and vertical wirings are drawn to be horizontally connected through a contact or horizontal wirings are used directly when they are horizontally connectable.
Recently, the automatic placement and wiring program for the three-metal layers has been highly developed so that the following semiconductor integrated circuit has been already developed: input, output or input/output terminals which have been conventionally formed by using contacts between the second metal layer and the third metal layer or the second metal layer, are now formed by using contacts between the second metal layer and a first metal layer formed thereunder or a first metal layer. The first metal layer is also used for forming an element.
FIG. 5 is a diagram showing a conventional design pattern obtained by the automatic placement and wiring using such an automatic placement and wiring program for three metal layers in a plurality of the standard cells each having the configuration as shown in FIG. 2. This design pattern is obtained by the automatic placement and wiring for a circuit as shown in FIG. 6. An inverter circuit 23A includes an input terminal 25A and output terminal 25B, and a NOR circuit 23B includes input terminals 25C, 25D and 25E and an output terminal 25F. A NOR circuit 23C includes input terminals 25G and 25H and an output terminal 25I, and a NOR circuit 23D includes input terminals 25J and 25K and an output terminal 25L. The terminals (25A, 25B, 25C, 25D, 25E, 25F, 25G, 25H, 25I, 25J, 25K and 25L) are horizontally aligned in a line as shown in FIG. 5.
The input terminal 25A of the inverter circuit 8A is connected with a standard cell 43A in another cell group through a wiring 21A, and the output terminal 25B with the input terminal 25C of the NOR circuit 23B through a wiring 24A. The input terminal 25D of the NOR circuit 23B is connected with a standard cell 43B through a wiring 21B, the input terminal 25E with a standard cell 43C through a wiring 21C, and the output terminal 25F with the input terminal 25K of the NOR circuit 23D through a wiring 24B. The input terminal 25G of the NOR circuit 23C is connected with the standard cell 43C through the wiring 21C, the input terminal 25H with a standard cell 43D through a wiring 21D, and the output terminal 25I with the input terminal 25J of the NOR circuit 23D through a wiring 24C. The output terminal 25L of the NOR circuit 23D is connected with a standard cell 44 through a wiring 22.
Broken lines in FIG. 5 indicate the horizontal wirings, which use a third metal layer. Dashed lines therein indicate the vertical wirings, which use a second metal layer. Double lines also indicate horizontal wirings, which use a first metal layer. Contacts for connecting the second metal layer (the vertical wirings) and the third metal layer (the horizontal wirings) with each other are indicated as 26A through 26D.
The wirings among the inverter circuit 23A and the NOR circuits 23B, 23C and 23I) will now be described. The output terminal 25B and the input terminal 25C are directly connected with each other through the wiring (24A) using the first metal layer, and the output terminal 25I and the input terminal 25J are directly connected with each other through the horizontal wiring (24C) also using the first metal layer. With regard to the connection between the input terminals 25E and 25G, vertical wirings drawn upward from the respective terminals are connected with each other through the contact 26A, a horizontal wiring using the third metal layer and the contact 26C. With regard to the connection between the output terminal 25F and the input terminal 25K, vertical wiring formed downward from the respective terminals are connected with each other through the contact 26B, the horizontal wiring 24B using the third metal layer and the contact 26D.
The wirings 21A, 21B, 21C, 21D and 22 are vertical wirings using the second metal layer.
In such a conventional configuration of the input, output or input/output terminals, adjacent terminals can disturb the placement of a horizontal wiring. Therefore, vertical wirings are required to be drawn upward or downward, and contacts are required to be formed in the same number as that of terminals for connecting the drawn vertical wirings with horizontal wirings. These requirements result in longer wirings and the decrease of the operation speed of a circuit. Further, since a plurality of connections are provided between a second metal layer and a third metal layer, a large number of contacts are required, resulting in degradation of the reliability and the yield.